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The SPI-4 Phase 2 (System Packet Interface Level 4 Phase 2) is a high-speed interconnection for 10 Gb/s aggregate bandwidth applications. It provides for packet and cell transfer in applications such as OC-192 ATM, Packet over Sonet/SDH, as well as 10 Gb/s Ethernet.

SLE's SPI-4 receiver and transmitter blocks provide a complete solution for the customers' applications; from physical layer bit de-skew through the link-layer protocol management. This includes all OIF required features for the full solution and some additional features for easier implementation and integration.

These full-featured designs provide the functionality and flexibility required to speed time-to-market.  

 SPI-4 Phase 2 Top Level Block Diagram:

Highlighted Features

• Conforms to Optical Internetworking Forum specification OIF-SPI4-02.0 System Packet Interface Level 4 Phase 2 standard
• Implementation is technology independent, currently available in 9 different technologies, portable to other technologies
• Fully testable synchronous design meets 1000 Mb/s per line
• Supports dynamic bit de-skew over full frequency range as well as static mode of operation
• Incorporates a fully digital design which is implemented in standard cell ASIC libraries using no custom cells, no analog components, no PLLs, and no DLLs
• Incorporates a proprietary real-time tuning feature which reduces the need for periodic training, increases usable bandwidth, and improves data integrity
• Features a high-speed digital SERDES for technology portability and faster time-to-market
• Manages up to 256 ports and supports calendar lengths up to 1024, allowing for uneven bandwidth allocation across channels
• Performs credit management and arbitration to ease core logic design and accelerate time-to-market
• Incorporates an asynchronous interface between the core logic design and the SPI-4 channel clock to ease core logic and accelerate time-to-market
• Allows for per-port configurable maxburst values creating maximum flexibility in bandwidth allocation
• Includes encrypted Verilog for the packet generator which, when added to a Verilog test bench, generates valid SPI-4 data packets to be transmitted over the channel
• Includes encrypted Verilog for the protocol checker which verifies the data being sent across the channel meets the OIF protocol standard
• Simple flow through user architecture allows for design and implementation flexibility and highly configurable operation
• Optimized for high-speed ASICs

More Information

Because interoperability is a fundamental requirement of today's high-speed interfaces, the SLE-developed SPI-4 Phase 2 core has been proven interoperable with the similar offerings from leading ASSP developers.

Using SLE's SPI-4.2 IP product offerings, designers can significantly reduce implementation costs and accelerate their time-to-market compared to in-house or full-custom design alternatives. See what our customers have said about working with SLE's IP and design team:SLE Customer Survey

SLE's SPI-4 Phase 2 is currently available in 9 different technologies and portable to many other technologies. They include:

SLE SPI-4.2 Customers

Some of SLE's SPI-4.2 customers include leading networking and computing companies. References are available upon request.